Structure Diagram for TRF: Trigger Efficiency Processor
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         An Introduction to the Structure Diagrams is available.
        NB  These links will be broken until the HTML Version of the Code is installed.
 
 
Introduction
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The TRF processor is designed to measure the trigger efficiency of the SNO
detector.  Its inputs are data sets in which the trigger signals themselves are
connected to the FECD (Slot 15 of Crate 17) and the detector is triggered
asynchronously off of a source (typically the laserball). The output of the TRF
processor is a TREF titles bank which holds the efficiencies and errors at each
in-time NHIT value measured for each NHIT trigger type.


Titles Banks Used
-----------------
 
 TREF  Trigger Efficiency Table

 TTRF  TTRF: Trigger Efficiency Calibration Control

 
 
 
Initialisation Routines
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TRF_INI
 

Execution Routines
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TRF_EXE

 
Termination Routines
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TRF_TRM