bank_trig
TRIG Trigger bank
======================
Contact: N. West, Oxford.
Revision History:-
================
3.01 D. Wark First version, data from Peter Wittich.
3.02 N. West Add Run Number + 5 spares.
Fix misordering of OWLN,OWLELO,OWLEHI
Description
-----------
Holds data from the global trigger.
Reference Links
---------------
None.
Structural Links
----------------
None.
Status Bits
-----------
Note: Any status bit parameters are defined to work with bit functions such as
IAND and BTEST.
Data Words
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Data types: B(bit), I, F, D(double), H(hollerith 4 char)
Wd Typ Mnem. Description
KTRIG_
+1 I TRIG_MASK Trigger mask, for bits see note 1 below.
+2 I N100LO - -
+3 I N100MED |
+4 I N100HI |
+5 I N20 | / Words 2-11 are the present trigger thresholds for
+6 I N20LB |----< the indicated trigger (see the SNO-STR-97-035) in
+7 I ESUMLO | \ DAC counts.
+8 I ESUMHI |
+9 I OWLN |
+10 I OWLELO |
+11 I OWLEHI --
+12 I N100LO_ZERO --
+13 I N100MED_ZERO |
+14 I N100HI_ZERO |
+15 I N20_ZERO | / Word 12-21 trigger zero offsets (i.e., the
+16 I N20LB_ZERO |--< difference between the value in word 2-11 above
+17 I ESUMLO_ZERO | \ and the value of word 12-21 for the given trigger
+18 I ESUMHI_ZERO | \ is the threshold for that trigger
+19 I OWLN_ZERO |
+20 I OWLELO_ZERO |
+21 I OWLEHI_ZERO --
+22 I PULSER_RATE Current setting of the MTCD pulser in frequency.
+23 I MTC_CSR MTCD control and status register, see note 2.
+24 I LKOUT_WIDTH Lockout width, see note 3.
+25 I PRESCALE_FRAC Prescale setting, see note 4.
+26 I GT_ID Global Trigger ID indicating the start of validity.
+27 I RUN_NUMBER Run number
+28 I Spare
.. I ..
+32 I ..
Notes
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1) Each bit set in the global trigger mask indicates a trigger that is
masked in. For a fuller description see SNO-STR-97-035. The bits are:
Trigger type Bit Description
NHIT100LO 0x00000001UL Low threshold, 100 ns wide trigger window
NHIT100MED 0x00000002UL med threshold, 100 ns wide trigger window
NHIT100HI 0x00000004UL you get the idea
NHIT20 0x00000008UL tube-to-tube programmable 20 ns wide trigger
NHIT20LB 0x00000010UL lookback version of 20 ns trigger
ESUMLO 0x00000020UL trigger on energy sum of low gain
ESUMHI 0x00000040UL trigger on energy sum of high gain
OWLN 0x00000080UL 100ns nhit trigger on outward looking tubes
OWLELO 0x00000100UL energy sum, low gain on outward tubes
OWLEHI 0x00000200UL energy sum, high gain on outward tubes
PULSE_GT 0x00000400UL pulser generated calibration trigger
PRESCALE 0x00000800UL Prescaled NHIT_100_LO trigger
PEDESTAL 0x00001000UL Pedestal calibration trigger
PONG 0x00002000UL GPS round-trip delay trigger
SYNC 0x00004000UL GPS synchronization trigger
EXT_ASYNC 0x00008000UL External trigger not synched to the 50 MHz
EXT2 0x00010000UL External synchronous trigger 2
EXT3 0x00020000UL and 3
EXT4 0x00040000UL and 4
EXT5 0x00080000UL and do forth.....
EXT6 0x00100000UL
EXT7 0x00200000UL
EXT8_PULSE_ASYNC 0x00400000UL ext trig. 8, also makes pulse_gt asynch.
SPECIAL_RAW 0x00800000UL Logical combination of up to 9 triggers
NCD 0x01000000UL Neutral Current Detector trigger
SOFT_GT 0x02000000UL Trigger forced from software
There is one more trigger bit that you cannot mask in but will appear in the
data stream, namely:
MISS_TRIG 0x04000000UL Missed trigger bit, i.e., an additional
trigger arrived after the trigger coin.
but before LOCKOUT.
2) The bits in the control and register status register are:
PED_EN 0x00000001UL Enable pedestal pulse
PULSE_EN 0x00000002UL Enable on-board calibration pulser
LOAD_ENPR 0x00000004UL Prescale load enable (toggle to load SCALE)
LOAD_ENPS 0x00000008UL Pulser load enable (toggle to load period)
LOAD_ENPW 0x00000010UL toggle to load pedestal width and coarse del
LOAD_ENLK 0x00000020UL toggle to load lockout width
ASYNC_EN 0x00000040UL enable generation of synclr on gt
RESYNC_EN 0x00000080UL generate synclr on gt counter 16-bit roll
TESTGT 0x00000100UL gt counter test mode
TEST50 0x00000200UL 50 MHz test mode
TEST10 0x00000400UL 10 MHz test mode
LOAD_ENGT 0x00000800UL toggle to load programmed gt count
LOAD_EN50 0x00001000UL toggle to load programmed 50 MHz setting
LOAD_EN10 0x00002000UL toggle to load programmed 10 MHz setting
TESTMEM1 0x00004000UL memory test mode 1
TESTMEM2 0x00008000UL memory test mode 2
FIFO_RESET 0x00010000UL reset all fifo pointers
The remaining bits specify which MTC/A DAC threshold to monitor.
For a fuller description see SNO-STR-97-035.
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