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/* Copyright (c) 2019, Anthony Latorre <tlatorre at uchicago>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option)
* any later version.
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <https://www.gnu.org/licenses/>.
*/
#ifndef DQXX_H
#define DQXX_H
#include "event.h"
#include "dict.h"
extern char dqxx_err[256];
/* bits used in the DQCH title bank. */
#define KDQCH_TABLE 10
/* PMT cable in (0), out or unknown tube type (1) */
#define KDQCH_B_PMT_CABLE 0x1
/* PMTIC channel resistor present (0), not present (1) */
#define KDQCH_B_PMTIC_RESISTOR 0x2
/* Channel sequencer enabled (0), disabled (1) */
#define KDQCH_B_SEQUENCER 0x4
/* 100ns trigger enabled (0), disabled (1) */
#define KDQCH_B_100NS 0x8
/* 20ns trigger enabled (0), disabled (1) */
#define KDQCH_B_20NS 0x10
/* 750 Ohm terminator OK (0), blown (1) */
#define KDQCH_B_750OHM 0x20
/* Qinj OK (0), malfunctioning i.e. Large/Small/Bad (1) */
#define KDQCH_B_QINJ 0x40
/* 100 ns trigger OK (0), dead (1) */
#define KDQCH_B_N100 0x80
/* 20 ns trigger OK (0), dead (1) */
#define KDQCH_B_N20 0x100
/* operational (0), not operational (1) */
#define KDQCH_B_NOT_OP 0x200
/* logical OR of bits 0-9 */
#define KDQCH_B_BAD 0x400
/* Bits 16-24 represent the voltage threshold, and bits 24-32 represent the
* voltage threshold zero. */
/* bits used in the DQCR title bank. */
#define KDQCR_TABLE 10
/* Crate present (0), not present (1) */
#define KDQCR_B_CRATE 0x1
/* MB present (0), not present (1) */
#define KDQCR_B_MB 0x2
/* PMTIC present (0), not present (1) */
#define KDQCR_B_PMTIC 0x4
/* DAQ readout (eCPU) online (0), offline (1) */
#define KDQCR_B_DAQ 0x8
/* Daughter cards all present (0), 4 bit mask of present DC.
* Channel i associated with DC at bit DC + i/8. */
#define KDQCR_B_DC 0x10
/* OR of bits 0-7, 2-15.
* This is deemed to mean 'slot operation', as it is an OR of crate, slot, db,
* etc. operational. */
#define KDQCR_B_SLOT_OP 0x100
/* GT mask for crate, i.e. is this crate receiving global triggers. */
#define KDQCR_B_GT 0x200
/* Crate on-line (i.e. is being read out by ECPU). */
#define KDQCR_B_CR_ONLINE 0x400
/* or of bit 0 (SNO crate present) and bits 16-31 (HV bits). */
#define KDQCR_B_CR_HV 0x800
/* HV relays all on (0), 4 bit mask of relays on. */
#define KDQCR_B_RELAY 0x1000
int dqxx_init(dict *db, event *ev);
#endif
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